1. Field of the Invention
The present invention relates in general to liquid crystal display devices and, in more particular, to a technique usefully applicable to an image signal drive unit (drain driver or drivers) of a liquid crystal display device with multilevel gradation/tone display abilities.
2. Description of the Related Art
Liquid crystal display devices of the active matrix type having an active element (e.g. thin-film transistor) on a per-pixel basis and driving this active element to perform a switching operation have widely been employed as the display device of a notebook personal computer or the like.
These active-matrix liquid crystal display (AMLCD) devices are such that due to application of an image signal voltage (gradation/tone voltage corresponding to display data, as will be referred to as gradation/tone voltage hereinafter) to a pixel electrode via such active element, any cross-talk is absent between respective pixels and thus, it is no longer necessary to employ “special” driving methods for prevention of crosstalk unlike simple-matrix liquid crystal display devices, thereby enabling successful achievement of multi-gradation-level or “gray-scale” display abilities.
As one of the active-matrix liquid crystal display devices, there is known a TFT liquid crystal display module, which comprises a liquid crystal display panel of the thin-film transistor (TFT) scheme, also called TFT-LCD panel, drain drivers as disposed on the upper side of the liquid crystal display panel, and gate drivers and an interface section as disposed along side faces of the liquid crystal display panel.
FIG. 24 is a block diagram showing a schematic configuration of one example of related art TFT liquid crystal display module.
As shown in FIG. 24, a plurality of drain drivers 130 are disposed along a long edge side of the liquid crystal display panel (TFT-LCD) 10 whereas a plurality of gate drivers 140 are laid out along a short edge side of the liquid crystal display panel 10.
Control signals that are output from a host computer side such as a personal computer and consist essentially of display data (image signal) of three primary colors of red (R), green (G) and blue (B), a clock signal(s), a display timing signal(s), and synchronization signals (horizontal sync signal and vertical sync signal) are input to a display control device (TFT controller) 110 via an interface connector.
A control signal(s) and display data and the like from the display control device 110 are input to each drain driver 130 via a TFT controller substrate 301 and drain driver substrate 302.
In addition, the control signal(s) from the display control device 110 will be input to each gate driver 140 through the TFT controller substrate 301 and a gate driver substrate 303.
Note that depiction of a wiring layer(s) on or over the TFT controller substrate is eliminated in FIG. 24.
Also note that although more than one wiring layer other than the wiring layer shown in FIG. 24 is also provided on the drain driver substrate and gate driver substrate, only four lines of wiring layers for the drain driver substrate 302 and only two lines of wiring layers for the gate driver substrate 303 are depicted in FIG. 24.
The drain drivers 130 and gate drivers 140 are constituted from semiconductor chips (ICs), wherein these semiconductor chips (ICs) are mounted on a film substrate by either the so-called tape carrier techniques or chip-on-film techniques.
As shown in FIG. 25 a wiring layer (COFA) is formed on the film substrate 310 from the periphery, wherein terminals (BUMP) being provided at the periphery of semiconductor chip (IC) are coupled by bonding to this wiring layer (COFA).
Here, drain driver terminals (BUMP) are typically provided along the peripheral portions thereof, one example of which is shown in FIG. 26.
As shown in FIG. 26, input terminals (BUMP2) are disposed along one side for enabling connection of wiring leads from the drain driver substrate 302 whereas output terminals (BUMP1) are disposed at either the remaining three sides or four peripheral portions including right and left spaces of a side along which the input terminals (BUMP2) are disposed.
Additionally output circuits 330 within the drain drivers corresponding to respective output terminals (BUMP1) are typically laid out into a linear array in a way identical to output terminal positions.
Note that such liquid crystal display device has been recited, for example, in Japanese Patent Laid-Open No. 281930/1997.
In recent years, in liquid crystal display devices such as TFT liquid crystal display modules, with the increasing demand for larger display screen sizes of liquid crystal display panels, they are in the tendency toward increase in pixel number of a liquid crystal display panel and also requirement for achievement of higher precision; and, in accordance therewith, gate signal lines and drain signal lines also increase in number resulting in a likewise increase in input/output terminal number of the drain drivers.
For instance, with an XGA-format liquid crystal display panel, the requisite number of drain signal lines is 3,072 (=1,024×3 (RGB)). Assuming that drain drivers with 384 output terminals are used, the required number of drain drivers in the XGA-LCD panel becomes as large as 8 (=3,072/384).
In contrast, with the quest for higher precision further advances up to UXGA specifications, the resultant number of drain signal lines is 4,800 (=1,600×3 (RGB)). As in the previous case, supposing that drain drivers with the 384 output terminal number are used, the required drain driver number in UXGA-LCD panels becomes 12.5 (=4,800/384).
In this way, the higher the precision of liquid crystal display panels, the greater the drain line number per liquid crystal display panel, resulting in an increase in number of drain drivers required.
Whereby the resulting load capacitance of the display control device 110 increases accordingly, resulting in occurrence of a problem as to an incapability to drive the drain drivers 130.
In order to prevent the number of drain drivers from changing even when a liquid crystal display panel increases in precision, it should be required to increase the output terminal number per drain driver.
Generally, semiconductor chips (ICs) making up the drain drivers are such that the outer shape thereof is like a laterally elongated plate shape, wherein if output terminals (BUMP) per drain driver increase in number then it becomes necessary to increase the length of a semiconductor chip (IC) along its lateral direction.
In addition, while semiconductor chips (ICs) are fabricated by cutaway processes after having formed a plurality of ones on a single semiconductor wafer, the greater the lateral directional length of semiconductor chips (ICs) with a further increased length in lateral direction thereof, the less the number of chips obtainable from a single wafer, resulting in an undesirable increase in price of a single semiconductor chip (IC).
Further, with laterally lengthened semiconductor chips (ICs) with a further increased length in the lateral direction thereof, there is an anxiety that excessive increase beyond the exposure range can take place when forming semiconductor chips (ICs) through the so-called step-and-repeat exposure process on the surface of a single semiconductor wafer.
To avoid this, it will be required to make use of exposure apparatus of high price, resulting in an increase in price of a single semiconductor chip (IC).
On the other hand, while liquid crystal display devices are under strict requirement for lower prices, there is a problem that the higher the semiconductor chip (IC) making up the drain driver 130, the higher the price of a liquid crystal display device.
In addition, with an increase in drain signal lines, there is a tendency to inevitable increase in pitch of the output terminals (BUMP1) of drain drivers 130; thus, there is a problem that probing becomes difficult during screening of semiconductor chips (ICs).
Furthermore, with such increase in drain signal lines, the circuit scale of a single drain driver 130 tends to grow larger; thus, there is a problem that a voltage drop-down due to the presence of wiring lead impedances within semiconductor chip (IC) becomes no longer negligible.